Integrated circuit manufacture requires wafers as a basic starting material. At the present time, the silicon wafers used in integrated circuit fabrication are prepared using a highly developed process which will be briefly described so that the invention can be better understood. Silicon ingots are grown using the well known Czochralski growth technique which puts a seed crystal into molten silicon and then withdraws the seed crystal as the ingot grows. Either or both the ingot and crucible containing the molten silicon are rotated during ingot growth. Device considerations require that the wafers be (100) oriented wafers. The ingot orientation during the ingot sawing process is critical if the wafers are to have the desired (100) orientation. After the ingot is grown, the seed and tail ends of the ingot are removed. The ingot is ground to the desired diameter and transferred to x-ray diffraction apparatus where the (110) orientation is located and marked along the ingot with a line. The ingot is then returned to a grinding machine, and a flat centered on the marked line is ground to a prescribed width. The ingot is maintained in a stationary position during the flat grinding process. Of course, a notch or other feature may be ground or otherwise formed rather than a flat. The flat or notch may be made with a tolerance of approximately 1 degree. The ingot is mounted on a carrier plate, and a test wafer cut so that the (100) orientation may be determined by x-ray diffraction. Some correction may be required, and several test wafers may have to be cut before the desired orientation is obtained. See, for example, Silicon Processing for the VLSI Era, Vol. 1, pp. 8-26, S. Wolf and R. N. Tauber, 1986, Lattice Press, for a description of ingot growth and wafer preparation.
The process described is adequate today for many purposes although it does have some drawbacks. For example, examination of two test wafers is generally required before the desired ingot orientation of .+-.30 minutes of arc is obtained. Tighter orientation requirements will generally require more test wafers. The procedure, because of the number of test wafers that must be examined to achieve the ingot desired (100) orientation, contributes to the wafer cost. It is probable that as wafer diameters increase beyond the, at present, most widely used 150 mm diameter, the costs associated with ingot alignment, including flat grinding, will increase even more. Furthermore, single diffraction x-ray apparatus has a resolution limit of approximately .+-.10 minutes of arc. Better resolution may be obtained by using a double diffraction system which is, of course, more complex and expensive than is a single diffraction system. Furthermore, in addition to the costs associated with present alignment tolerances, future integrated circuits using smaller design rules, for example, 0.25 .mu.m or smaller, than are commonly used in high volume manufacture today will require better control of wafer orientation than is required today. The requirement for better wafer orientation control is imposed by device considerations. For example, excessive roughness in thin gate oxides on epitaxial silicon can be related to wafer (100) misorientation and is undesirable. The oxide roughness may lead to, for example, current leakage through the gate oxide. Other examples of the need for better wafer orientation of both (100) and (110) exist. An orientation tolerance of .+-. a minute of arc will likely be required for (100).